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LTC2382-16
14
238216f
APPLICATIONS INFORMATION
SAMPLING RATE (kHz)
0
100
200
300
400
500
0
POWER
SUPPL
Y
CURRENT
(mA)
2.5
2
1
0.5
1.5
3
238216 F11
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 10 shows
that the LTC2382-16 achieves a typical SNR of 92dB at a
500kHz sampling rate with a 20kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD
VVV
V
N
=
++
+
20
23
4
1
22
2
log
…
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2382-16 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2382-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Power Supply Sequencing
The LTC2382-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2382-16
has a power-on-reset (POR) circuit that will reset the
LTC2382-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
reenters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20μs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
Figure 11. Power Supply Current of the
LTC2382-16 vs Sampling Rate
TIMING AND CONTROL
CNV Timing
The LTC2382-16 conversion is controlled by CNV. A rising
edge on CNV will start a conversion. Once a conversion has
been initiated, it cannot be restarted until the conversion
is complete. For optimum performance, CNV should be
driven by a clean low jitter signal. Converter status is
indicated by the BUSY output which remains high while the
conversion is in progress. To ensure that no errors occur
in the digitized results, any additional transitions on CNV
should occur within 40ns from the start of the conversion
or after the conversion has been completed.
ACQUISITION
A proprietary sampling architecture allows the LTC2382-16
to begin acquiring the input signal for the next conversion
750ns after the start of the current conversion. This extends
the acquisition time to 1.25μs, easing settling requirements
and allowing the use of extremely low power ADC drivers.
(Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2382-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 1.5μs.
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制造商:Linear Technology 功能描述:ADC 16-Bit 1Msps Low Power SPI DFN16